-----------------------------------------------------------------------------
--
-- The register allocator
--
-- (c) The University of Glasgow 2004
--
-----------------------------------------------------------------------------

{-
The algorithm is roughly:

  1) Compute strongly connected components of the basic block list.

  2) Compute liveness (mapping from pseudo register to
     point(s) of death?).

  3) Walk instructions in each basic block.  We keep track of
        (a) Free real registers (a bitmap?)
        (b) Current assignment of temporaries to machine registers and/or
            spill slots (call this the "assignment").
        (c) Partial mapping from basic block ids to a virt-to-loc mapping.
            When we first encounter a branch to a basic block,
            we fill in its entry in this table with the current mapping.

     For each instruction:
        (a) For each temporary *read* by the instruction:
            If the temporary does not have a real register allocation:
                - Allocate a real register from the free list.  If
                  the list is empty:
                  - Find a temporary to spill.  Pick one that is
                    not used in this instruction (ToDo: not
                    used for a while...)
                  - generate a spill instruction
                - If the temporary was previously spilled,
                  generate an instruction to read the temp from its spill loc.
            (optimisation: if we can see that a real register is going to
            be used soon, then don't use it for allocation).

        (b) For each real register clobbered by this instruction:
            If a temporary resides in it,
                If the temporary is live after this instruction,
                    Move the temporary to another (non-clobbered & free) reg,
                    or spill it to memory.  Mark the temporary as residing
                    in both memory and a register if it was spilled (it might
                    need to be read by this instruction).

            (ToDo: this is wrong for jump instructions?)

            We do this after step (a), because if we start with
               movq v1, %rsi
            which is an instruction that clobbers %rsi, if v1 currently resides
            in %rsi we want to get
               movq %rsi, %freereg
               movq %rsi, %rsi     -- will disappear
            instead of
               movq %rsi, %freereg
               movq %freereg, %rsi

        (c) Update the current assignment

        (d) If the instruction is a branch:
              if the destination block already has a register assignment,
                Generate a new block with fixup code and redirect the
                jump to the new block.
              else,
                Update the block id->assignment mapping with the current
                assignment.

        (e) Delete all register assignments for temps which are read
            (only) and die here.  Update the free register list.

        (f) Mark all registers clobbered by this instruction as not free,
            and mark temporaries which have been spilled due to clobbering
            as in memory (step (a) marks then as in both mem & reg).

        (g) For each temporary *written* by this instruction:
            Allocate a real register as for (b), spilling something
            else if necessary.
                - except when updating the assignment, drop any memory
                  locations that the temporary was previously in, since
                  they will be no longer valid after this instruction.

        (h) Delete all register assignments for temps which are
            written and die here (there should rarely be any).  Update
            the free register list.

        (i) Rewrite the instruction with the new mapping.

        (j) For each spilled reg known to be now dead, re-add its stack slot
            to the free list.

-}

module GHC.CmmToAsm.Reg.Linear (
        regAlloc,
        module  GHC.CmmToAsm.Reg.Linear.Base,
        module  GHC.CmmToAsm.Reg.Linear.Stats
  ) where

import GHC.Prelude

import GHC.CmmToAsm.Reg.Linear.State
import GHC.CmmToAsm.Reg.Linear.Base
import GHC.CmmToAsm.Reg.Linear.StackMap
import GHC.CmmToAsm.Reg.Linear.FreeRegs
import GHC.CmmToAsm.Reg.Linear.Stats
import GHC.CmmToAsm.Reg.Linear.JoinToTargets
import qualified GHC.CmmToAsm.Reg.Linear.PPC     as PPC
import qualified GHC.CmmToAsm.Reg.Linear.X86     as X86
import qualified GHC.CmmToAsm.Reg.Linear.X86_64  as X86_64
import qualified GHC.CmmToAsm.Reg.Linear.AArch64 as AArch64
import qualified GHC.CmmToAsm.Reg.Linear.RV64    as RV64
import qualified GHC.CmmToAsm.Reg.Linear.LA64    as LA64
import GHC.CmmToAsm.Reg.Target
import GHC.CmmToAsm.Reg.Liveness
import GHC.CmmToAsm.Reg.Utils
import GHC.CmmToAsm.Instr
import GHC.CmmToAsm.Config
import GHC.CmmToAsm.Format
import GHC.CmmToAsm.Types
import GHC.Platform.Reg
import GHC.Platform.Reg.Class (RegArch (..), registerArch)
import qualified GHC.Platform.Reg.Class.Separate  as Separate
import qualified GHC.Platform.Reg.Class.Unified   as Unified
import qualified GHC.Platform.Reg.Class.NoVectors as NoVectors

import GHC.Cmm.BlockId
import GHC.Cmm.Dataflow.Label
import GHC.Cmm

import GHC.Data.Graph.Directed
import GHC.Types.Unique
import GHC.Types.Unique.FM
import GHC.Types.Unique.DSM
import GHC.Types.Unique.Set
import GHC.Utils.Outputable
import GHC.Utils.Panic
import GHC.Platform

import Data.Containers.ListUtils
import Data.Maybe
import Data.List (sortOn)
import Control.Monad

-- -----------------------------------------------------------------------------
-- Top level of the register allocator

-- Allocate registers
regAlloc
        :: Instruction instr
        => NCGConfig
        -> LiveCmmDecl statics instr
        -> UniqDSM ( NatCmmDecl statics instr
                   , Maybe Int  -- number of extra stack slots required,
                                -- beyond maxSpillSlots
                   , Maybe RegAllocStats
                   )

regAlloc :: forall instr statics.
Instruction instr =>
NCGConfig
-> LiveCmmDecl statics instr
-> UniqDSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
regAlloc NCGConfig
_ (CmmData Section
sec statics
d)
        = (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
-> UniqDSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall a. a -> UniqDSM a
forall (m :: * -> *) a. Monad m => a -> m a
return
                ( Section -> statics -> NatCmmDecl statics instr
forall d h g. Section -> d -> GenCmmDecl d h g
CmmData Section
sec statics
d
                , Maybe Int
forall a. Maybe a
Nothing
                , Maybe RegAllocStats
forall a. Maybe a
Nothing )

regAlloc NCGConfig
_ (CmmProc (LiveInfo LabelMap RawCmmStatics
info [BlockId]
_ BlockMap Regs
_ BlockMap IntSet
_) CLabel
lbl [GlobalRegUse]
live [])
        = (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
-> UniqDSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall a. a -> UniqDSM a
forall (m :: * -> *) a. Monad m => a -> m a
return ( LabelMap RawCmmStatics
-> CLabel
-> [GlobalRegUse]
-> ListGraph instr
-> NatCmmDecl statics instr
forall d h g.
h -> CLabel -> [GlobalRegUse] -> g -> GenCmmDecl d h g
CmmProc LabelMap RawCmmStatics
info CLabel
lbl [GlobalRegUse]
live ([GenBasicBlock instr] -> ListGraph instr
forall i. [GenBasicBlock i] -> ListGraph i
ListGraph [])
                 , Maybe Int
forall a. Maybe a
Nothing
                 , Maybe RegAllocStats
forall a. Maybe a
Nothing )

regAlloc NCGConfig
config (CmmProc LiveInfo
static CLabel
lbl [GlobalRegUse]
live [SCC (LiveBasicBlock instr)]
sccs)
        | LiveInfo LabelMap RawCmmStatics
info entry_ids :: [BlockId]
entry_ids@(BlockId
first_id:[BlockId]
_) BlockMap Regs
block_live BlockMap IntSet
_ <- LiveInfo
static
        = do
                -- do register allocation on each component.
                !(!final_blocks, !stats, !stack_use)
                        <- NCGConfig
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([GenBasicBlock instr], RegAllocStats, Int)
forall instr.
Instruction instr =>
NCGConfig
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc NCGConfig
config [BlockId]
entry_ids BlockMap Regs
block_live [SCC (LiveBasicBlock instr)]
sccs

                -- make sure the block that was first in the input list
                --      stays at the front of the output
                let !final_blocks' = (GenBasicBlock instr -> Bool)
-> [GenBasicBlock instr] -> [GenBasicBlock instr]
forall b a. Ord b => (a -> b) -> [a] -> [a]
sortOn ((BlockId -> BlockId -> Bool
forall a. Eq a => a -> a -> Bool
/= BlockId
first_id) (BlockId -> Bool)
-> (GenBasicBlock instr -> BlockId) -> GenBasicBlock instr -> Bool
forall b c a. (b -> c) -> (a -> b) -> a -> c
. GenBasicBlock instr -> BlockId
forall i. GenBasicBlock i -> BlockId
blockId) [GenBasicBlock instr]
final_blocks

                let max_spill_slots = NCGConfig -> Int
maxSpillSlots NCGConfig
config
                    extra_stack
                      | Int
stack_use Int -> Int -> Bool
forall a. Ord a => a -> a -> Bool
> Int
max_spill_slots
                      = Int -> Maybe Int
Int -> Maybe Int
forall a. a -> Maybe a
Just (Int -> Maybe Int) -> Int -> Maybe Int
forall a b. (a -> b) -> a -> b
$! Int
stack_use Int -> Int -> Int
forall a. Num a => a -> a -> a
- Int
max_spill_slots
                      | Bool
otherwise
                      = Maybe Int
forall a. Maybe a
Nothing

                return  ( CmmProc info lbl live (ListGraph final_blocks')
                        , extra_stack
                        , Just stats)

-- bogus. to make non-exhaustive match warning go away.
regAlloc NCGConfig
_ (CmmProc LiveInfo
_ CLabel
_ [GlobalRegUse]
_ [SCC (LiveBasicBlock instr)]
_)
        = String
-> UniqDSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall a. HasCallStack => String -> a
panic String
"RegAllocLinear.regAlloc: no match"


-- -----------------------------------------------------------------------------
-- Linear sweep to allocate registers


-- | Do register allocation on some basic blocks.
--   But be careful to allocate a block in an SCC only if it has
--   an entry in the block map or it is the first block.
--
linearRegAlloc
        :: forall instr. (Instruction instr)
        => NCGConfig
        -> [BlockId] -- ^ entry points
        -> BlockMap Regs
              -- ^ live regs on entry to each basic block
        -> [SCC (LiveBasicBlock instr)]
              -- ^ instructions annotated with "deaths"
        -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)

linearRegAlloc :: forall instr.
Instruction instr =>
NCGConfig
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc NCGConfig
config [BlockId]
entry_ids BlockMap Regs
block_live [SCC (LiveBasicBlock instr)]
sccs
 = case Platform -> Arch
platformArch Platform
platform of
      Arch
ArchX86        -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: X86.FreeRegs)
      Arch
ArchX86_64     -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: X86_64.FreeRegs)
      Arch
ArchS390X      -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchS390X"
      Arch
ArchPPC        -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: PPC.FreeRegs)
      ArchARM ArmISA
_ [ArmISAExt]
_ ArmABI
_  -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchARM"
      Arch
ArchAArch64    -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: AArch64.FreeRegs)
      ArchPPC_64 PPC_64ABI
_   -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: PPC.FreeRegs)
      Arch
ArchAlpha      -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchAlpha"
      Arch
ArchMipseb     -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchMipseb"
      Arch
ArchMipsel     -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchMipsel"
      Arch
ArchRISCV64    -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: RV64.FreeRegs)
      Arch
ArchLoongArch64 -> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: LA64.FreeRegs)
      Arch
ArchJavaScript -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchJavaScript"
      Arch
ArchWasm32     -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchWasm32"
      Arch
ArchUnknown    -> String -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. HasCallStack => String -> a
panic String
"linearRegAlloc ArchUnknown"
 where
  go :: (FR regs, Outputable regs)
     => regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
  go :: forall regs.
(FR regs, Outputable regs) =>
regs -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
go regs
f = NCGConfig
-> regs
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
NCGConfig
-> freeRegs
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc' NCGConfig
config regs
f [BlockId]
entry_ids BlockMap Regs
block_live [SCC (LiveBasicBlock instr)]
sccs
  platform :: Platform
platform = NCGConfig -> Platform
ncgPlatform NCGConfig
config

-- | Constraints on the instruction instances used by the
-- linear allocator.
type OutputableRegConstraint freeRegs instr =
        (FR freeRegs, Outputable freeRegs, Instruction instr)

linearRegAlloc'
        :: OutputableRegConstraint freeRegs instr
        => NCGConfig
        -> freeRegs
        -> [BlockId]                    -- ^ entry points
        -> BlockMap Regs              -- ^ live regs on entry to each basic block
        -> [SCC (LiveBasicBlock instr)] -- ^ instructions annotated with "deaths"
        -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)

linearRegAlloc' :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
NCGConfig
-> freeRegs
-> [BlockId]
-> BlockMap Regs
-> [SCC (LiveBasicBlock instr)]
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc' NCGConfig
config freeRegs
initFreeRegs [BlockId]
entry_ids BlockMap Regs
block_live [SCC (LiveBasicBlock instr)]
sccs
 = (DUniqSupply
 -> DUniqResult ([NatBasicBlock instr], RegAllocStats, Int))
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. (DUniqSupply -> DUniqResult a) -> UniqDSM a
UDSM ((DUniqSupply
  -> DUniqResult ([NatBasicBlock instr], RegAllocStats, Int))
 -> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int))
-> (DUniqSupply
    -> DUniqResult ([NatBasicBlock instr], RegAllocStats, Int))
-> UniqDSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ \DUniqSupply
us -> do
    let !(BlockAssignment freeRegs
_, !StackMap
stack, !RegAllocStats
stats, ![NatBasicBlock instr]
blocks, DUniqSupply
us') =
            NCGConfig
-> BlockAssignment freeRegs
-> freeRegs
-> RegMap Loc
-> StackMap
-> DUniqSupply
-> RegM freeRegs [NatBasicBlock instr]
-> (BlockAssignment freeRegs, StackMap, RegAllocStats,
    [NatBasicBlock instr], DUniqSupply)
forall freeRegs a.
NCGConfig
-> BlockAssignment freeRegs
-> freeRegs
-> RegMap Loc
-> StackMap
-> DUniqSupply
-> RegM freeRegs a
-> (BlockAssignment freeRegs, StackMap, RegAllocStats, a,
    DUniqSupply)
runR NCGConfig
config BlockAssignment freeRegs
forall freeRegs. BlockAssignment freeRegs
emptyBlockAssignment freeRegs
initFreeRegs RegMap Loc
forall a. RegMap a
emptyRegMap StackMap
emptyStackMap DUniqSupply
us
                (RegM freeRegs [NatBasicBlock instr]
 -> (BlockAssignment freeRegs, StackMap, RegAllocStats,
     [NatBasicBlock instr], DUniqSupply))
-> RegM freeRegs [NatBasicBlock instr]
-> (BlockAssignment freeRegs, StackMap, RegAllocStats,
    [NatBasicBlock instr], DUniqSupply)
forall a b. (a -> b) -> a -> b
$ [BlockId]
-> BlockMap Regs
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
[BlockId]
-> BlockMap Regs
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
entry_ids BlockMap Regs
block_live [] [SCC (LiveBasicBlock instr)]
sccs
     in ([NatBasicBlock instr], RegAllocStats, Int)
-> DUniqSupply
-> DUniqResult ([NatBasicBlock instr], RegAllocStats, Int)
forall a. a -> DUniqSupply -> (# a, DUniqSupply #)
DUniqResult ([NatBasicBlock instr]
blocks, RegAllocStats
stats, StackMap -> Int
getStackUse StackMap
stack) DUniqSupply
us'


linearRA_SCCs :: OutputableRegConstraint freeRegs instr
              => [BlockId]
              -> BlockMap Regs
              -> [NatBasicBlock instr]
              -> [SCC (LiveBasicBlock instr)]
              -> RegM freeRegs [NatBasicBlock instr]

linearRA_SCCs :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
[BlockId]
-> BlockMap Regs
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
_ BlockMap Regs
_ [NatBasicBlock instr]
blocksAcc []
        = [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr])
-> [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall a b. (a -> b) -> a -> b
$ [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a]
reverse [NatBasicBlock instr]
blocksAcc

linearRA_SCCs [BlockId]
entry_ids BlockMap Regs
block_live [NatBasicBlock instr]
blocksAcc (AcyclicSCC LiveBasicBlock instr
block : [SCC (LiveBasicBlock instr)]
sccs)
 = do   blocks' <- BlockMap Regs
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
processBlock BlockMap Regs
block_live LiveBasicBlock instr
block
        linearRA_SCCs entry_ids block_live
                ((reverse blocks') ++ blocksAcc)
                sccs

linearRA_SCCs [BlockId]
entry_ids BlockMap Regs
block_live [NatBasicBlock instr]
blocksAcc (CyclicSCC [LiveBasicBlock instr]
blocks : [SCC (LiveBasicBlock instr)]
sccs)
 = do
        blockss' <- [BlockId]
-> BlockMap Regs
-> [LiveBasicBlock instr]
-> RegM freeRegs [[NatBasicBlock instr]]
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
[BlockId]
-> BlockMap Regs
-> [GenBasicBlock (LiveInstr instr)]
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap Regs
block_live [LiveBasicBlock instr]
blocks
        linearRA_SCCs entry_ids block_live
                (reverse (concat blockss') ++ blocksAcc)
                sccs

{- from John Dias's patch 2008/10/16:
   The linear-scan allocator sometimes allocates a block
   before allocating one of its predecessors, which could lead to
   inconsistent allocations. Make it so a block is only allocated
   if a predecessor has set the "incoming" assignments for the block, or
   if it's the procedure's entry block.

   BL 2009/02: Careful. If the assignment for a block doesn't get set for
   some reason then this function will loop. We should probably do some
   more sanity checking to guard against this eventuality.
-}

process :: forall freeRegs instr. (OutputableRegConstraint freeRegs instr)
        => [BlockId]
        -> BlockMap Regs
        -> [GenBasicBlock (LiveInstr instr)]
        -> RegM freeRegs [[NatBasicBlock instr]]
process :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
[BlockId]
-> BlockMap Regs
-> [GenBasicBlock (LiveInstr instr)]
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap Regs
block_live =
    \[GenBasicBlock (LiveInstr instr)]
blocks -> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
go [GenBasicBlock (LiveInstr instr)]
blocks [] ([NatBasicBlock instr] -> [[NatBasicBlock instr]]
forall a. a -> [a]
forall (m :: * -> *) a. Monad m => a -> m a
return []) Bool
False
  where
    go :: [GenBasicBlock (LiveInstr instr)]
       -> [GenBasicBlock (LiveInstr instr)]
       -> [[NatBasicBlock instr]]
       -> Bool
       -> RegM freeRegs [[NatBasicBlock instr]]
    go :: [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
go [] []         [[NatBasicBlock instr]]
accum Bool
_madeProgress
      = [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]])
-> [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a b. (a -> b) -> a -> b
$ [[NatBasicBlock instr]] -> [[NatBasicBlock instr]]
forall a. [a] -> [a]
reverse [[NatBasicBlock instr]]
accum

    go [] [GenBasicBlock (LiveInstr instr)]
next_round [[NatBasicBlock instr]]
accum Bool
madeProgress
      | Bool -> Bool
not Bool
madeProgress
          {- BUGS: There are so many unreachable blocks in the code the warnings are overwhelming.
             pprTrace "RegAlloc.Linear.Main.process: no progress made, bailing out."
                (  text "Unreachable blocks:"
                $$ vcat (map ppr next_round)) -}
      = [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]])
-> [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a b. (a -> b) -> a -> b
$ [[NatBasicBlock instr]] -> [[NatBasicBlock instr]]
forall a. [a] -> [a]
reverse [[NatBasicBlock instr]]
accum

      | Bool
otherwise
      = [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
go [GenBasicBlock (LiveInstr instr)]
next_round [] [[NatBasicBlock instr]]
accum Bool
False

    go (b :: GenBasicBlock (LiveInstr instr)
b@(BasicBlock BlockId
id [LiveInstr instr]
_) : [GenBasicBlock (LiveInstr instr)]
blocks) [GenBasicBlock (LiveInstr instr)]
next_round [[NatBasicBlock instr]]
accum Bool
madeProgress
      = do
          block_assig <- RegM freeRegs (BlockAssignment freeRegs)
forall freeRegs. RegM freeRegs (BlockAssignment freeRegs)
getBlockAssigR
          if isJust (lookupBlockAssignment id block_assig) || id `elem` entry_ids
            then do b' <- processBlock block_live b
                    go blocks next_round (b' : accum) True

            else do go blocks (b : next_round) accum madeProgress


-- | Do register allocation on this basic block
--
processBlock
        :: OutputableRegConstraint freeRegs instr
        => BlockMap Regs              -- ^ live regs on entry to each basic block
        -> LiveBasicBlock instr         -- ^ block to do register allocation on
        -> RegM freeRegs [NatBasicBlock instr]   -- ^ block with registers allocated

processBlock :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
processBlock BlockMap Regs
block_live (BasicBlock BlockId
id [LiveInstr instr]
instrs)
 = do   -- pprTraceM "processBlock" $ text "" $$ ppr (BasicBlock id instrs)
        BlockId -> BlockMap Regs -> RegM freeRegs ()
forall freeRegs.
FR freeRegs =>
BlockId -> BlockMap Regs -> RegM freeRegs ()
initBlock BlockId
id BlockMap Regs
block_live

        (instrs', fixups)
                <- BlockMap Regs
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
linearRA BlockMap Regs
block_live BlockId
id [LiveInstr instr]
instrs
        -- pprTraceM "blockResult" $ ppr (instrs', fixups)
        return  $ BasicBlock id instrs' : fixups


-- | Load the freeregs and current reg assignment into the RegM state
--      for the basic block with this BlockId.
initBlock :: FR freeRegs
          => BlockId -> BlockMap Regs -> RegM freeRegs ()
initBlock :: forall freeRegs.
FR freeRegs =>
BlockId -> BlockMap Regs -> RegM freeRegs ()
initBlock BlockId
id BlockMap Regs
block_live
 = do   platform    <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
        block_assig <- getBlockAssigR
        case lookupBlockAssignment id block_assig of
                -- no prior info about this block: we must consider
                -- any fixed regs to be allocated, but we can ignore
                -- virtual regs (presumably this is part of a loop,
                -- and we'll iterate again).  The assignment begins
                -- empty.
                Maybe (freeRegs, RegMap Loc)
Nothing
                 -> do  -- pprTrace "initFreeRegs" (text $ show initFreeRegs) (return ())
                        case BlockId -> BlockMap Regs -> Maybe Regs
forall a. BlockId -> LabelMap a -> Maybe a
mapLookup BlockId
id BlockMap Regs
block_live of
                          Maybe Regs
Nothing ->
                            freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR    (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform)
                          Just Regs
live ->
                            freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (freeRegs -> RegM freeRegs ()) -> freeRegs -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$ (freeRegs -> RealReg -> freeRegs)
-> freeRegs -> [RealReg] -> freeRegs
forall b a. (b -> a -> b) -> b -> [a] -> b
forall (t :: * -> *) b a.
Foldable t =>
(b -> a -> b) -> b -> t a -> b
foldl' ((RealReg -> freeRegs -> freeRegs)
-> freeRegs -> RealReg -> freeRegs
forall a b c. (a -> b -> c) -> b -> a -> c
flip ((RealReg -> freeRegs -> freeRegs)
 -> freeRegs -> RealReg -> freeRegs)
-> (RealReg -> freeRegs -> freeRegs)
-> freeRegs
-> RealReg
-> freeRegs
forall a b. (a -> b) -> a -> b
$ Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform) (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform)
                                                  (UniqSet RealReg -> [RealReg]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet (UniqSet RealReg -> [RealReg]) -> UniqSet RealReg -> [RealReg]
forall a b. (a -> b) -> a -> b
$ UniqSet RegWithFormat -> UniqSet RealReg
takeRealRegs (UniqSet RegWithFormat -> UniqSet RealReg)
-> UniqSet RegWithFormat -> UniqSet RealReg
forall a b. (a -> b) -> a -> b
$ Regs -> UniqSet RegWithFormat
getRegs Regs
live)
                            -- See Note [Unique Determinism and code generation]
                        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR       RegMap Loc
forall a. RegMap a
emptyRegMap

                -- load info about register assignments leading into this block.
                Just (freeRegs
freeregs, RegMap Loc
assig)
                 -> do  freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR    freeRegs
freeregs
                        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR       RegMap Loc
assig


-- | Do allocation for a sequence of instructions.
linearRA
        :: forall freeRegs instr. (OutputableRegConstraint freeRegs instr)
        => BlockMap Regs                      -- ^ map of what vregs are live on entry to each block.
        -> BlockId                              -- ^ id of the current block, for debugging.
        -> [LiveInstr instr]                    -- ^ liveness annotated instructions in this block.
        -> RegM freeRegs
                ( [instr]                       --   instructions after register allocation
                , [NatBasicBlock instr])        --   fresh blocks of fixup code.
linearRA :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
linearRA BlockMap Regs
block_live BlockId
block_id = [instr]
-> [NatBasicBlock instr]
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
go [] []
  where
    go :: [instr]                              -- accumulator for instructions already processed.
       -> [NatBasicBlock instr]                -- accumulator for blocks of fixup code.
       -> [LiveInstr instr]                    -- liveness annotated instructions in this block.
       -> RegM freeRegs
               ( [instr]                       --   instructions after register allocation
               , [NatBasicBlock instr] )       --   fresh blocks of fixup code.
    go :: [instr]
-> [NatBasicBlock instr]
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
go ![instr]
accInstr ![NatBasicBlock instr]
accFixups [] = do
        ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ( [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
accInstr               -- instrs need to be returned in the correct order.
               , [NatBasicBlock instr]
accFixups )                    -- it doesn't matter what order the fixup blocks are returned in.

    go [instr]
accInstr [NatBasicBlock instr]
accFixups (LiveInstr instr
instr:[LiveInstr instr]
instrs) = do
        (accInstr', new_fixups) <- BlockMap Regs
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
raInsn BlockMap Regs
block_live [instr]
accInstr BlockId
block_id LiveInstr instr
instr
        go accInstr' (new_fixups ++ accFixups) instrs

-- | Do allocation for a single instruction.
raInsn
        :: OutputableRegConstraint freeRegs instr
        => BlockMap Regs                      -- ^ map of what vregs are love on entry to each block.
        -> [instr]                              -- ^ accumulator for instructions already processed.
        -> BlockId                              -- ^ the id of the current block, for debugging
        -> LiveInstr instr                      -- ^ the instr to have its regs allocated, with liveness info.
        -> RegM freeRegs
                ( [instr]                       -- new instructions
                , [NatBasicBlock instr])        -- extra fixup blocks

raInsn :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
raInsn BlockMap Regs
_     [instr]
new_instrs BlockId
_ (LiveInstr InstrSR instr
ii Maybe Liveness
Nothing)
        | Just Int
n        <- InstrSR instr -> Maybe Int
forall instr. Instruction instr => instr -> Maybe Int
takeDeltaInstr InstrSR instr
ii
        = do    Int -> RegM freeRegs ()
forall freeRegs. Int -> RegM freeRegs ()
setDeltaR Int
n
                ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
new_instrs, [])

raInsn BlockMap Regs
_     [instr]
new_instrs BlockId
_ (LiveInstr ii :: InstrSR instr
ii@(Instr instr
i) Maybe Liveness
Nothing)
        | InstrSR instr -> Bool
forall instr. Instruction instr => instr -> Bool
isMetaInstr InstrSR instr
ii
        = ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return (instr
i instr -> [instr] -> [instr]
forall a. a -> [a] -> [a]
: [instr]
new_instrs, [])


raInsn BlockMap Regs
block_live [instr]
new_instrs BlockId
id (LiveInstr (Instr instr
instr) (Just Liveness
live))
 = do
    platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
    assig    <- getAssigR

    -- If we have a reg->reg move between virtual registers, where the
    -- src register is not live after this instruction, and the dst
    -- register does not already have an assignment,
    -- and the source register is assigned to a register, not to a spill slot,
    -- then we can eliminate the instruction.
    -- (we can't eliminate it if the source register is on the stack, because
    --  we do not want to use one spill slot for different virtual registers)
    case takeRegRegMoveInstr platform instr of
        Just (Reg
src,Reg
dst)  | Just Format
fmt <- Reg -> Regs -> Maybe Format
lookupReg Reg
src (Liveness -> Regs
liveDieRead Liveness
live),
                          Reg -> Bool
isVirtualReg Reg
dst,
                          Bool -> Bool
not (Reg
dst Reg -> RegMap Loc -> Bool
forall key elt. Uniquable key => key -> UniqFM key elt -> Bool
`elemUFM` RegMap Loc
assig),
                          Reg -> Bool
isRealReg Reg
src Bool -> Bool -> Bool
|| Reg -> RegMap Loc -> Bool
isInReg Reg
src RegMap Loc
assig -> do
           case Reg
src of
              RegReal RealReg
rr -> RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> Reg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM RegMap Loc
assig Reg
dst (VLoc -> Format -> Loc
Loc (RealReg -> VLoc
InReg RealReg
rr) Format
fmt))
                -- if src is a fixed reg, then we just map dest to this
                -- reg in the assignment.  src must be an allocatable reg,
                -- otherwise it wouldn't be in r_dying.
              Reg
_virt -> case RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM key elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
src of
                         Maybe Loc
Nothing -> String -> RegM freeRegs ()
forall a. HasCallStack => String -> a
panic String
"raInsn"
                         Just Loc
loc ->
                           RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> Reg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM (RegMap Loc -> Reg -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> UniqFM key elt
delFromUFM RegMap Loc
assig Reg
src) Reg
dst Loc
loc)

           -- we have eliminated this instruction
          {-
          freeregs <- getFreeRegsR
          assig <- getAssigR
          pprTrace "raInsn" (text "ELIMINATED: " <> docToSDoc (pprInstr instr)
                        $$ ppr r_dying <+> ppr w_dying $$ text (show freeregs) $$ ppr assig) $ do
          -}
           ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
new_instrs, [])

        Maybe (Reg, Reg)
_ -> BlockMap Regs
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
genRaInsn BlockMap Regs
block_live [instr]
new_instrs BlockId
id instr
instr
                        ((RegWithFormat -> Reg) -> [RegWithFormat] -> [Reg]
forall a b. (a -> b) -> [a] -> [b]
map RegWithFormat -> Reg
regWithFormat_reg ([RegWithFormat] -> [Reg]) -> [RegWithFormat] -> [Reg]
forall a b. (a -> b) -> a -> b
$ UniqSet RegWithFormat -> [RegWithFormat]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet (UniqSet RegWithFormat -> [RegWithFormat])
-> UniqSet RegWithFormat -> [RegWithFormat]
forall a b. (a -> b) -> a -> b
$ Regs -> UniqSet RegWithFormat
getRegs (Regs -> UniqSet RegWithFormat) -> Regs -> UniqSet RegWithFormat
forall a b. (a -> b) -> a -> b
$ Liveness -> Regs
liveDieRead Liveness
live)
                        ((RegWithFormat -> Reg) -> [RegWithFormat] -> [Reg]
forall a b. (a -> b) -> [a] -> [b]
map RegWithFormat -> Reg
regWithFormat_reg ([RegWithFormat] -> [Reg]) -> [RegWithFormat] -> [Reg]
forall a b. (a -> b) -> a -> b
$ UniqSet RegWithFormat -> [RegWithFormat]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet (UniqSet RegWithFormat -> [RegWithFormat])
-> UniqSet RegWithFormat -> [RegWithFormat]
forall a b. (a -> b) -> a -> b
$ Regs -> UniqSet RegWithFormat
getRegs (Regs -> UniqSet RegWithFormat) -> Regs -> UniqSet RegWithFormat
forall a b. (a -> b) -> a -> b
$ Liveness -> Regs
liveDieWrite Liveness
live)
                        -- See Note [Unique Determinism and code generation]

raInsn BlockMap Regs
_ [instr]
_ BlockId
_ LiveInstr instr
instr
        = do
            platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
            let instr' = (instr -> SDoc) -> LiveInstr instr -> LiveInstr SDoc
forall a b. (a -> b) -> LiveInstr a -> LiveInstr b
forall (f :: * -> *) a b. Functor f => (a -> b) -> f a -> f b
fmap (Platform -> instr -> SDoc
forall instr. Instruction instr => Platform -> instr -> SDoc
pprInstr Platform
platform) LiveInstr instr
instr
            pprPanic "raInsn" (text "no match for:" <> ppr instr')

-- ToDo: what can we do about
--
--     R1 = x
--     jump I64[x] // [R1]
--
-- where x is mapped to the same reg as R1.  We want to coalesce x and
-- R1, but the register allocator doesn't know whether x will be
-- assigned to again later, in which case x and R1 should be in
-- different registers.  Right now we assume the worst, and the
-- assignment to R1 will clobber x, so we'll spill x into another reg,
-- generating another reg->reg move.


isInReg :: Reg -> RegMap Loc -> Bool
isInReg :: Reg -> RegMap Loc -> Bool
isInReg Reg
src RegMap Loc
assig
  | Just (Loc (InReg RealReg
_) Format
_) <- RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM key elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
src
  = Bool
True
  | Bool
otherwise
  = Bool
False


genRaInsn :: forall freeRegs instr.
             (OutputableRegConstraint freeRegs instr)
          => BlockMap Regs
          -> [instr]
          -> BlockId
          -> instr
          -> [Reg]
          -> [Reg]
          -> RegM freeRegs ([instr], [NatBasicBlock instr])

genRaInsn :: forall freeRegs instr.
OutputableRegConstraint freeRegs instr =>
BlockMap Regs
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
genRaInsn BlockMap Regs
block_live [instr]
new_instrs BlockId
block_id instr
instr [Reg]
r_dying [Reg]
w_dying = do
-- pprTraceM "genRaInsn" $ ppr (block_id, instr)
  platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
  case regUsageOfInstr platform instr of { RU [RegWithFormat]
read [RegWithFormat]
written ->
    do
    let real_written :: [RealReg]
real_written = [ RealReg
rr                          | RegWithFormat {regWithFormat_reg :: RegWithFormat -> Reg
regWithFormat_reg = RegReal RealReg
rr} <- [RegWithFormat]
written ]
    let virt_written :: [VirtualRegWithFormat]
virt_written = [ VirtualReg -> Format -> VirtualRegWithFormat
VirtualRegWithFormat VirtualReg
vr Format
fmt | RegWithFormat (RegVirtual VirtualReg
vr) Format
fmt              <- [RegWithFormat]
written ]

    -- we don't need to do anything with real registers that are
    -- only read by this instr.  (the list is typically ~2 elements,
    -- so using nub isn't a problem).
    let virt_read :: [VirtualRegWithFormat]
        virt_read :: [VirtualRegWithFormat]
virt_read = (VirtualRegWithFormat -> VirtualReg)
-> [VirtualRegWithFormat] -> [VirtualRegWithFormat]
forall b a. Ord b => (a -> b) -> [a] -> [a]
nubOrdOn VirtualRegWithFormat -> VirtualReg
virtualRegWithFormat_reg [ VirtualReg -> Format -> VirtualRegWithFormat
VirtualRegWithFormat VirtualReg
vr Format
fmt | RegWithFormat (RegVirtual VirtualReg
vr) Format
fmt <- [RegWithFormat]
read ]

--     do
--         let real_read       = nub [ rr      | (RegReal rr) <- read]
--         freeregs <- getFreeRegsR
--         assig    <- getAssigR

--         pprTraceM "genRaInsn"
--                 (          text "block        = " <+> ppr block_id
--                         $$ text "instruction  = " <+> ppr instr
--                         $$ text "r_dying      = " <+> ppr r_dying
--                         $$ text "w_dying      = " <+> ppr w_dying
--                         $$ text "read         = " <+> ppr real_read    <+> ppr virt_read
--                         $$ text "written      = " <+> ppr real_written <+> ppr virt_written
--                         $$ text "freeregs     = " <+> ppr freeregs
--                         $$ text "assign       = " <+> ppr assig)

    -- (a), (b) allocate real regs for all regs read by this instruction.
    (r_spills, r_allocd) <-
        Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
True{-reading-} [VirtualRegWithFormat]
virt_read [] [] [VirtualRegWithFormat]
virt_read

    -- (c) save any temporaries which will be clobbered by this instruction
    clobber_saves <- saveClobberedTemps real_written r_dying

    -- (d) Update block map for new destinations
    -- NB. do this before removing dead regs from the assignment, because
    -- these dead regs might in fact be live in the jump targets (they're
    -- only dead in the code that follows in the current basic block).
    (fixup_blocks, adjusted_instr)
        <- joinToTargets block_live block_id instr

--     when (not $ null fixup_blocks) $ pprTraceM "genRA:FixBlocks" $ ppr fixup_blocks

    -- Debugging - show places where the reg alloc inserted
    -- assignment fixup blocks.
    -- when (not $ null fixup_blocks) $
    --    pprTrace "fixup_blocks" (ppr fixup_blocks) (return ())

    -- (e) Delete all register assignments for temps which are read
    --     (only) and die here.  Update the free register list.
    releaseRegs r_dying

    -- (f) Mark regs which are clobbered as unallocatable
    clobberRegs real_written

    -- (g) Allocate registers for temporaries *written* (only)
    (w_spills, w_allocd) <-
        allocateRegsAndSpill False{-writing-} virt_written [] [] virt_written

    -- (h) Release registers for temps which are written here and not
    -- used again.
    releaseRegs w_dying

    let
        -- (i) Patch the instruction
        patch_map :: UniqFM Reg Reg
        patch_map
                = UniqFM VirtualReg Reg -> UniqFM Reg Reg
forall elt. UniqFM VirtualReg elt -> UniqFM Reg elt
toRegMap (UniqFM VirtualReg Reg -> UniqFM Reg Reg)
-> UniqFM VirtualReg Reg -> UniqFM Reg Reg
forall a b. (a -> b) -> a -> b
$ -- Cast key from VirtualReg to Reg
                             -- See Note [UniqFM and the register allocator]
                  [(VirtualReg, Reg)] -> UniqFM VirtualReg Reg
forall key elt. Uniquable key => [(key, elt)] -> UniqFM key elt
listToUFM
                        [ (VirtualRegWithFormat -> VirtualReg
virtualRegWithFormat_reg VirtualRegWithFormat
vr, RealReg -> Reg
RegReal RealReg
rr)
                        | (VirtualRegWithFormat
vr, RealReg
rr) <- [VirtualRegWithFormat]
-> [RealReg] -> [(VirtualRegWithFormat, RealReg)]
forall a b. [a] -> [b] -> [(a, b)]
zip [VirtualRegWithFormat]
virt_read    [RealReg]
r_allocd
                                   [(VirtualRegWithFormat, RealReg)]
-> [(VirtualRegWithFormat, RealReg)]
-> [(VirtualRegWithFormat, RealReg)]
forall a. [a] -> [a] -> [a]
++ [VirtualRegWithFormat]
-> [RealReg] -> [(VirtualRegWithFormat, RealReg)]
forall a b. [a] -> [b] -> [(a, b)]
zip [VirtualRegWithFormat]
virt_written [RealReg]
w_allocd ]

        patched_instr :: instr
        patched_instr
                = Platform -> instr -> (Reg -> Reg) -> instr
forall instr.
(Instruction instr, HasDebugCallStack) =>
Platform -> instr -> (Reg -> Reg) -> instr
patchRegsOfInstr Platform
platform instr
adjusted_instr Reg -> Reg
patchLookup

        patchLookup :: Reg -> Reg
        patchLookup Reg
x
                = case UniqFM Reg Reg -> Reg -> Maybe Reg
forall key elt. Uniquable key => UniqFM key elt -> key -> Maybe elt
lookupUFM UniqFM Reg Reg
patch_map Reg
x of
                        Maybe Reg
Nothing -> Reg
x
                        Just Reg
y  -> Reg
y

    -- (j) free up stack slots for dead spilled regs
    -- TODO (can't be bothered right now)

    -- erase reg->reg moves where the source and destination are the same.
    --  If the src temp didn't die in this instr but happened to be allocated
    --  to the same real reg as the destination, then we can erase the move anyway.
    let squashed_instr  = case Platform -> instr -> Maybe (Reg, Reg)
forall instr.
Instruction instr =>
Platform -> instr -> Maybe (Reg, Reg)
takeRegRegMoveInstr Platform
platform instr
patched_instr of
                                Just (Reg
src, Reg
dst)
                                 | Reg
src Reg -> Reg -> Bool
forall a. Eq a => a -> a -> Bool
== Reg
dst   -> []
                                Maybe (Reg, Reg)
_               -> [instr
patched_instr]

    -- On the use of @reverse@ below.
    -- Since we can have spills and reloads produce multiple instructions
    -- we need to ensure they are emitted in the correct order.  We used to only
    -- emit single instructions in mkSpill/mkReload/mkRegRegMove.
    -- As such order of spills and reloads didn't matter.  However,  with
    -- multiple instructions potentially issued by those functions we need to be
    -- careful to not break execution order. Reversing the spills (clobber will
    -- also spill), will ensure they are emitted in the right order.
    --
    -- See also Ticket 19910 for changing the return type from [] to OrdList.

    -- For debugging, uncomment the follow line and the mkComment lines.
    -- u <- getUniqueR
    let code = [[instr]] -> [instr]
forall (t :: * -> *) a. Foldable t => t [a] -> [a]
concat [ --  mkComment (text "<genRaInsn(" <> ppr u <> text ")>")
                        -- ,mkComment (text "<genRaInsn(" <> ppr u <> text "):squashed>")]
                        [instr]
squashed_instr
                        -- ,mkComment (text "<genRaInsn(" <> ppr u <> text "):w_spills>")
                      , [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
w_spills
                        -- ,mkComment (text "<genRaInsn(" <> ppr u <> text "):r_spills>")
                      , [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
r_spills
                        -- ,mkComment (text "<genRaInsn(" <> ppr u <> text "):clobber_saves>")
                      , [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
clobber_saves
                        -- ,mkComment (text "<genRaInsn(" <> ppr u <> text "):new_instrs>")
                      , [instr]
new_instrs
                        -- ,mkComment (text "</genRaInsn(" <> ppr u <> text ")>")
                      ]

--    pprTrace "patched-code" ((vcat $ map (docToSDoc . pprInstr) code)) $ do
--    pprTrace "patched-fixup" ((ppr fixup_blocks)) $ do

    return (code, fixup_blocks)

  }

-- -----------------------------------------------------------------------------
-- releaseRegs

releaseRegs :: FR freeRegs => [Reg] -> RegM freeRegs ()
releaseRegs :: forall freeRegs. FR freeRegs => [Reg] -> RegM freeRegs ()
releaseRegs [Reg]
regs = do
  platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
  assig <- getAssigR
  free <- getFreeRegsR

  let loop RegMap Loc
assig !freeRegs
free [] = do RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR RegMap Loc
assig; freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR freeRegs
free; () -> RegM freeRegs ()
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ()
      loop RegMap Loc
assig !freeRegs
free (RegReal RealReg
rr : [Reg]
rs) = RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop RegMap Loc
assig (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
rr freeRegs
free) [Reg]
rs
      loop RegMap Loc
assig !freeRegs
free (Reg
r:[Reg]
rs) =
         case RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM key elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
r of
         Just (Loc (InBoth RealReg
real Int
_) Format
_) ->
           RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> UniqFM key elt
delFromUFM RegMap Loc
assig Reg
r)
                (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
real freeRegs
free) [Reg]
rs
         Just (Loc (InReg RealReg
real) Format
_) ->
           RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> UniqFM key elt
delFromUFM RegMap Loc
assig Reg
r)
                (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
real freeRegs
free) [Reg]
rs
         Maybe Loc
_ ->
           RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> UniqFM key elt
delFromUFM RegMap Loc
assig Reg
r) freeRegs
free [Reg]
rs
  loop assig free regs

-- -----------------------------------------------------------------------------
-- Clobber real registers

-- For each temp in a register that is going to be clobbered:
--      - if the temp dies after this instruction, do nothing
--      - otherwise, put it somewhere safe (another reg if possible,
--              otherwise spill and record InBoth in the assignment).
--      - for allocateRegs on the temps *read*,
--      - clobbered regs are allocatable.
--
--      for allocateRegs on the temps *written*,
--        - clobbered regs are not allocatable.
--

saveClobberedTemps
        :: forall instr freeRegs.
           (Instruction instr, FR freeRegs)
        => [RealReg]             -- ^ real registers clobbered by this instruction
        -> [Reg]                 -- ^ registers which are no longer live after this instruction,
                                 -- because read for the last time
        -> RegM freeRegs [instr] -- return: instructions to spill any temps that will
                                 -- be clobbered.

saveClobberedTemps :: forall instr freeRegs.
(Instruction instr, FR freeRegs) =>
[RealReg] -> [Reg] -> RegM freeRegs [instr]
saveClobberedTemps [] [Reg]
_
        = [instr] -> RegM freeRegs [instr]
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return []

saveClobberedTemps [RealReg]
clobbered [Reg]
dying
 = do
        assig   <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
        (assig',instrs) <- nonDetStrictFoldUFM_DirectlyM maybe_spill (assig,[]) assig
        setAssigR assig'
        return $ -- mkComment (text "<saveClobberedTemps>") ++
                 instrs
--              ++ mkComment (text "</saveClobberedTemps>")
   where
     -- Unique represents the VirtualReg
     -- Here we separate the cases which we do want to spill from these we don't.
     maybe_spill :: Unique
                 -> (RegMap Loc,[instr])
                 -> Loc
                 -> RegM freeRegs (RegMap Loc,[instr])
     maybe_spill :: Unique
-> (RegMap Loc, [instr])
-> Loc
-> RegM freeRegs (RegMap Loc, [instr])
maybe_spill !Unique
temp !(RegMap Loc
assig,[instr]
instrs) !Loc
loc =
        case Loc
loc of
                -- This is non-deterministic but we do not
                -- currently support deterministic code-generation.
                -- See Note [Unique Determinism and code generation]
                Loc (InReg RealReg
reg) Format
fmt
                    | (RealReg -> Bool) -> [RealReg] -> Bool
forall (t :: * -> *) a. Foldable t => (a -> Bool) -> t a -> Bool
any (RealReg -> RealReg -> Bool
realRegsAlias RealReg
reg) [RealReg]
clobbered
                    , Unique
temp Unique -> [Unique] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`notElem` (Reg -> Unique) -> [Reg] -> [Unique]
forall a b. (a -> b) -> [a] -> [b]
map Reg -> Unique
forall a. Uniquable a => a -> Unique
getUnique [Reg]
dying
                    -> Unique
-> (RegMap Loc, [instr])
-> RealRegUsage
-> RegM freeRegs (RegMap Loc, [instr])
clobber Unique
temp (RegMap Loc
assig,[instr]
instrs) (RealReg -> Format -> RealRegUsage
RealRegUsage RealReg
reg Format
fmt)
                Loc
_ -> (RegMap Loc, [instr]) -> RegM freeRegs (RegMap Loc, [instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return (RegMap Loc
assig,[instr]
instrs)

     -- See Note [UniqFM and the register allocator]
     clobber :: Unique -> (RegMap Loc,[instr]) -> RealRegUsage -> RegM freeRegs (RegMap Loc,[instr])
     clobber :: Unique
-> (RegMap Loc, [instr])
-> RealRegUsage
-> RegM freeRegs (RegMap Loc, [instr])
clobber Unique
temp (RegMap Loc
assig,[instr]
instrs) (RealRegUsage RealReg
reg Format
fmt)
       = do config <- RegM freeRegs NCGConfig
forall a. RegM a NCGConfig
getConfig
            platform <- getPlatform

            freeRegs <- getFreeRegsR
            let regclass = Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg
                freeRegs_thisClass = Platform -> RegClass -> freeRegs -> [RealReg]
forall freeRegs.
FR freeRegs =>
Platform -> RegClass -> freeRegs -> [RealReg]
frGetFreeRegs Platform
platform RegClass
regclass freeRegs
freeRegs

            case filter (`notElem` clobbered) freeRegs_thisClass of

              -- (1) we have a free reg of the right class that isn't
              -- clobbered by this instruction; use it to save the
              -- clobbered value.
              (RealReg
my_reg : [RealReg]
_) -> do
                  freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform RealReg
my_reg freeRegs
freeRegs)

                  let new_assign :: RegMap Loc
new_assign = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall {k} (key :: k) elt.
UniqFM key elt -> Unique -> elt -> UniqFM key elt
addToUFM_Directly RegMap Loc
assig Unique
temp (VLoc -> Format -> Loc
Loc (RealReg -> VLoc
InReg RealReg
my_reg) Format
fmt)
                  let instr :: instr
instr = NCGConfig -> Format -> Reg -> Reg -> instr
forall instr.
(Instruction instr, HasDebugCallStack) =>
NCGConfig -> Format -> Reg -> Reg -> instr
mkRegRegMoveInstr NCGConfig
config Format
fmt
                                  (RealReg -> Reg
RegReal RealReg
reg) (RealReg -> Reg
RegReal RealReg
my_reg)

                  (RegMap Loc, [instr]) -> RegM freeRegs (RegMap Loc, [instr])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return (RegMap Loc
new_assign,(instr
instr instr -> [instr] -> [instr]
forall a. a -> [a] -> [a]
: [instr]
instrs))

              -- (2) no free registers: spill the value
              [] -> do

                  (spill, slot)   <- RegWithFormat -> Unique -> RegM freeRegs ([instr], Int)
forall instr freeRegs.
Instruction instr =>
RegWithFormat -> Unique -> RegM freeRegs ([instr], Int)
spillR (Reg -> Format -> RegWithFormat
RegWithFormat (RealReg -> Reg
RegReal RealReg
reg) Format
fmt) Unique
temp

                  -- record why this reg was spilled for profiling
                  recordSpill (SpillClobber temp)

                  let new_assign  = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall {k} (key :: k) elt.
UniqFM key elt -> Unique -> elt -> UniqFM key elt
addToUFM_Directly RegMap Loc
assig Unique
temp (VLoc -> Format -> Loc
Loc (RealReg -> Int -> VLoc
InBoth RealReg
reg Int
slot) Format
fmt)

                  return (new_assign, (spill ++ instrs))




-- | Mark all these real regs as allocated,
--      and kick out their vreg assignments.
--
clobberRegs :: FR freeRegs => [RealReg] -> RegM freeRegs ()
clobberRegs :: forall freeRegs. FR freeRegs => [RealReg] -> RegM freeRegs ()
clobberRegs []
        = () -> RegM freeRegs ()
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ()

clobberRegs [RealReg]
clobbered
 = do   platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
        freeregs <- getFreeRegsR

        let allRegClasses =
               case Arch -> RegArch
registerArch (Platform -> Arch
platformArch Platform
platform) of
                 RegArch
Unified   ->   [RegClass]
Unified.allRegClasses
                 RegArch
Separate  ->  [RegClass]
Separate.allRegClasses
                 RegArch
NoVectors -> [RegClass]
NoVectors.allRegClasses
            allFreeRegs = (RegClass -> [RealReg]) -> [RegClass] -> [RealReg]
forall m a. Monoid m => (a -> m) -> [a] -> m
forall (t :: * -> *) m a.
(Foldable t, Monoid m) =>
(a -> m) -> t a -> m
foldMap (\ RegClass
rc -> Platform -> RegClass -> freeRegs -> [RealReg]
forall freeRegs.
FR freeRegs =>
Platform -> RegClass -> freeRegs -> [RealReg]
frGetFreeRegs Platform
platform RegClass
rc freeRegs
freeregs) [RegClass]
allRegClasses

        let extra_clobbered = [ RealReg
r | RealReg
r <- [RealReg]
clobbered, RealReg
r RealReg -> [RealReg] -> Bool
forall a. Eq a => a -> [a] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`elem` [RealReg]
allFreeRegs ]

        setFreeRegsR $! foldl' (flip $ frAllocateReg platform) freeregs extra_clobbered

        -- setFreeRegsR $! foldl' (flip $ frAllocateReg platform) freeregs clobbered

        assig           <- getAssigR
        setAssigR $! clobber assig (nonDetUFMToList assig)
          -- This is non-deterministic but we do not
          -- currently support deterministic code-generation.
          -- See Note [Unique Determinism and code generation]

   where
        -- if the temp was InReg and clobbered, then we will have
        -- saved it in saveClobberedTemps above.  So the only case
        -- we have to worry about here is InBoth.  Note that this
        -- also catches temps which were loaded up during allocation
        -- of read registers, not just those saved in saveClobberedTemps.

        clobber :: RegMap Loc -> [(Unique,Loc)] -> RegMap Loc
        clobber :: RegMap Loc -> [(Unique, Loc)] -> RegMap Loc
clobber RegMap Loc
assig []
                = RegMap Loc
assig

        clobber RegMap Loc
assig ((Unique
temp, Loc (InBoth RealReg
reg Int
slot) Format
regFmt) : [(Unique, Loc)]
rest)
                | (RealReg -> Bool) -> [RealReg] -> Bool
forall (t :: * -> *) a. Foldable t => (a -> Bool) -> t a -> Bool
any (RealReg -> RealReg -> Bool
realRegsAlias RealReg
reg) [RealReg]
clobbered
                = RegMap Loc -> [(Unique, Loc)] -> RegMap Loc
clobber (RegMap Loc -> Unique -> Loc -> RegMap Loc
forall {k} (key :: k) elt.
UniqFM key elt -> Unique -> elt -> UniqFM key elt
addToUFM_Directly RegMap Loc
assig Unique
temp (VLoc -> Format -> Loc
Loc (Int -> VLoc
InMem Int
slot) Format
regFmt)) [(Unique, Loc)]
rest

        clobber RegMap Loc
assig ((Unique, Loc)
_:[(Unique, Loc)]
rest)
                = RegMap Loc -> [(Unique, Loc)] -> RegMap Loc
clobber RegMap Loc
assig [(Unique, Loc)]
rest

-- -----------------------------------------------------------------------------
-- allocateRegsAndSpill

-- Why are we performing a spill?
data SpillLoc = ReadMem StackSlot Format -- reading from register only in memory
              | WriteNew                 -- writing to a new variable
              | WriteMem                 -- writing to register only in memory
-- Note that ReadNew is not valid, since you don't want to be reading
-- from an uninitialized register.  We also don't need the location of
-- the register in memory, since that will be invalidated by the write.
-- Technically, we could coalesce WriteNew and WriteMem into a single
-- entry as well. -- EZY

-- This function does several things:
--   For each temporary referred to by this instruction,
--   we allocate a real register (spilling another temporary if necessary).
--   We load the temporary up from memory if necessary.
--   We also update the register assignment in the process, and
--   the list of free registers and free stack slots.

allocateRegsAndSpill
        :: forall freeRegs instr. (FR freeRegs, Instruction instr)
        => Bool               -- True <=> reading (load up spilled regs)
        -> [VirtualRegWithFormat] -- don't push these out
        -> [instr]            -- spill insns
        -> [RealReg]          -- real registers allocated (accum.)
        -> [VirtualRegWithFormat] -- temps to allocate
        -> RegM freeRegs ( [instr] , [RealReg])

allocateRegsAndSpill :: forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
_       [VirtualRegWithFormat]
_    [instr]
spills [RealReg]
alloc []
        = ([instr], [RealReg]) -> RegM freeRegs ([instr], [RealReg])
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
spills, [RealReg] -> [RealReg]
forall a. [a] -> [a]
reverse [RealReg]
alloc)

allocateRegsAndSpill Bool
reading [VirtualRegWithFormat]
keep [instr]
spills [RealReg]
alloc (r :: VirtualRegWithFormat
r@(VirtualRegWithFormat VirtualReg
vr Format
vrFmt):[VirtualRegWithFormat]
rs)
 = do   assig <- RegMap Loc -> UniqFM VirtualReg Loc
forall elt. UniqFM Reg elt -> UniqFM VirtualReg elt
toVRegMap (RegMap Loc -> UniqFM VirtualReg Loc)
-> RegM freeRegs (RegMap Loc)
-> RegM freeRegs (UniqFM VirtualReg Loc)
forall (f :: * -> *) a b. Functor f => (a -> b) -> f a -> f b
<$> RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
        -- pprTraceM "allocateRegsAndSpill:assig" (ppr (r:rs) $$ ppr assig)
        -- See Note [UniqFM and the register allocator]
        let doSpill = Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> VirtualRegWithFormat
-> [VirtualRegWithFormat]
-> UniqFM VirtualReg Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> VirtualRegWithFormat
-> [VirtualRegWithFormat]
-> UniqFM VirtualReg Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill Bool
reading [VirtualRegWithFormat]
keep [instr]
spills [RealReg]
alloc VirtualRegWithFormat
r [VirtualRegWithFormat]
rs UniqFM VirtualReg Loc
assig
        case lookupUFM assig vr of
                -- case (1a): already in a register
                Just (Loc (InReg RealReg
my_reg) Format
in_reg_fmt) -> do
                  -- (RF1) from Note [Allocated register formats]:
                  -- writes redefine the format the register is used at.
                  Bool -> RegM freeRegs () -> RegM freeRegs ()
forall (f :: * -> *). Applicative f => Bool -> f () -> f ()
when (Bool -> Bool
not Bool
reading Bool -> Bool -> Bool
&& Format
vrFmt Format -> Format -> Bool
forall a. Eq a => a -> a -> Bool
/= Format
in_reg_fmt) (RegM freeRegs () -> RegM freeRegs ())
-> RegM freeRegs () -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$
                    RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> RegM freeRegs ()) -> RegMap Loc -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$ UniqFM VirtualReg Loc -> RegMap Loc
forall elt. UniqFM VirtualReg elt -> UniqFM Reg elt
toRegMap (UniqFM VirtualReg Loc -> RegMap Loc)
-> UniqFM VirtualReg Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$
                      UniqFM VirtualReg Loc -> VirtualReg -> Loc -> UniqFM VirtualReg Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM UniqFM VirtualReg Loc
assig VirtualReg
vr (VLoc -> Format -> Loc
Loc (RealReg -> VLoc
InReg RealReg
my_reg) Format
vrFmt)
                  Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualRegWithFormat]
keep [instr]
spills (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualRegWithFormat]
rs

                -- case (1b): already in a register (and memory)
                Just (Loc (InBoth RealReg
my_reg Int
_) Format
_) -> do
                  -- NB1. if we're writing this register, update its assignment to be
                  -- InReg, because the memory value is no longer valid.
                  -- NB2. This is why we must process written registers here, even if they
                  -- are also read by the same instruction.
                  Bool -> RegM freeRegs () -> RegM freeRegs ()
forall (f :: * -> *). Applicative f => Bool -> f () -> f ()
when (Bool -> Bool
not Bool
reading) (RegM freeRegs () -> RegM freeRegs ())
-> RegM freeRegs () -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$
                    RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> RegM freeRegs ()) -> RegMap Loc -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$ UniqFM VirtualReg Loc -> RegMap Loc
forall elt. UniqFM VirtualReg elt -> UniqFM Reg elt
toRegMap (UniqFM VirtualReg Loc -> RegMap Loc)
-> UniqFM VirtualReg Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$
                      UniqFM VirtualReg Loc -> VirtualReg -> Loc -> UniqFM VirtualReg Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM UniqFM VirtualReg Loc
assig VirtualReg
vr (VLoc -> Format -> Loc
Loc (RealReg -> VLoc
InReg RealReg
my_reg) Format
vrFmt)
                  Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> [VirtualRegWithFormat]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualRegWithFormat]
keep [instr]
spills (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualRegWithFormat]
rs

                -- Not already in a register, so we need to find a free one...
                Just (Loc (InMem Int
slot) Format
memFmt)
                   | Bool
reading   -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill (Int -> Format -> SpillLoc
ReadMem Int
slot Format
memFmt)
                   | Bool
otherwise -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill SpillLoc
WriteMem
                Maybe Loc
Nothing | Bool
reading   ->
                   String -> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a. HasCallStack => String -> SDoc -> a
pprPanic String
"allocateRegsAndSpill: Cannot read from uninitialized register" (VirtualReg -> SDoc
forall a. Outputable a => a -> SDoc
ppr VirtualReg
vr)
                   -- NOTE: if the input to the NCG contains some
                   -- unreachable blocks with junk code, this panic
                   -- might be triggered.  Make sure you only feed
                   -- sensible code into the NCG.  In GHC.Cmm.Pipeline we
                   -- call removeUnreachableBlocks at the end for this
                   -- reason.

                        | Bool
otherwise -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill SpillLoc
WriteNew

-- | Given a virtual reg find a preferred real register.
-- The preferred register is simply the first one the variable
-- was assigned to (if any). This way when we allocate for a loop
-- variables are likely to end up in the same registers at the
-- end and start of the loop, avoiding redundant reg-reg moves.
-- Note: I tried returning a list of past assignments, but that
-- turned out to barely matter.
findPrefRealReg :: VirtualReg -> RegM freeRegs (Maybe RealReg)
findPrefRealReg :: forall freeRegs. VirtualReg -> RegM freeRegs (Maybe RealReg)
findPrefRealReg VirtualReg
vreg = do
  bassig <- RegM freeRegs (BlockAssignment freeRegs)
forall freeRegs. RegM freeRegs (BlockAssignment freeRegs)
getBlockAssigR :: RegM freeRegs (BlockAssignment freeRegs)
  return $ lookupFirstUsed vreg bassig

-- reading is redundant with reason, but we keep it around because it's
-- convenient and it maintains the recursive structure of the allocator. -- EZY
allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr)
                        => Bool
                        -> [VirtualRegWithFormat]
                        -> [instr]
                        -> [RealReg]
                        -> VirtualRegWithFormat
                        -> [VirtualRegWithFormat]
                        -> UniqFM VirtualReg Loc
                        -> SpillLoc
                        -> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill :: forall freeRegs instr.
(FR freeRegs, Instruction instr) =>
Bool
-> [VirtualRegWithFormat]
-> [instr]
-> [RealReg]
-> VirtualRegWithFormat
-> [VirtualRegWithFormat]
-> UniqFM VirtualReg Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill Bool
reading [VirtualRegWithFormat]
keep [instr]
spills [RealReg]
alloc r :: VirtualRegWithFormat
r@(VirtualRegWithFormat VirtualReg
vr Format
vrFmt) [VirtualRegWithFormat]
rs UniqFM VirtualReg Loc
assig SpillLoc
spill_loc
 = do   platform <- RegM freeRegs Platform
forall a. RegM a Platform
getPlatform
        freeRegs <- getFreeRegsR
        let regclass = Arch -> VirtualReg -> RegClass
classOfVirtualReg (Platform -> Arch
platformArch Platform
platform) VirtualReg
vr
            freeRegs_thisClass = Platform -> RegClass -> freeRegs -> [RealReg]
forall freeRegs.
FR freeRegs =>
Platform -> RegClass -> freeRegs -> [RealReg]
frGetFreeRegs Platform
platform RegClass
regclass freeRegs
freeRegs :: [RealReg]

        -- Can we put the variable into a register it already was?
        pref_reg <- findPrefRealReg vr

        case freeRegs_thisClass of
         -- case (2): we have a free register
         (RealReg
first_free : [RealReg]
_) ->
           do   let !final_reg :: RealReg
final_reg
                        | Just RealReg
reg <- Maybe RealReg
pref_reg
                        , RealReg
reg RealReg -> [RealReg] -> Bool
forall a. Eq a => a -> [a] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`elem` [RealReg]
freeRegs_thisClass
                        = RealReg
reg
                        | Bool
otherwise
                        = RealReg
first_free

                spills'   <- VirtualRegWithFormat
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
VirtualRegWithFormat
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualRegWithFormat
r SpillLoc
spill_loc RealReg
final_reg [instr]
spills

                setAssigR $ toRegMap
                          $ (addToUFM assig vr $! newLocation spill_loc $ RealRegUsage final_reg vrFmt)
                setFreeRegsR $  frAllocateReg platform final_reg freeRegs

                allocateRegsAndSpill reading keep spills' (final_reg : alloc) rs


          -- case (3): we need to push something out to free up a register
         [] ->
           do   let inRegOrBoth :: VLoc -> Bool
inRegOrBoth (InReg RealReg
_) = Bool
True
                    inRegOrBoth (InBoth RealReg
_ Int
_) = Bool
True
                    inRegOrBoth VLoc
_ = Bool
False
                let candidates' :: UniqFM VirtualReg Loc
                    candidates' :: UniqFM VirtualReg Loc
candidates' =
                      (UniqFM VirtualReg Loc -> [VirtualReg] -> UniqFM VirtualReg Loc)
-> [VirtualReg] -> UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc
forall a b c. (a -> b -> c) -> b -> a -> c
flip UniqFM VirtualReg Loc -> [VirtualReg] -> UniqFM VirtualReg Loc
forall key (f :: * -> *) elt.
(Uniquable key, Foldable f) =>
UniqFM key elt -> f key -> UniqFM key elt
delListFromUFM ((VirtualRegWithFormat -> VirtualReg)
-> [VirtualRegWithFormat] -> [VirtualReg]
forall a b. (a -> b) -> [a] -> [b]
forall (f :: * -> *) a b. Functor f => (a -> b) -> f a -> f b
fmap VirtualRegWithFormat -> VirtualReg
virtualRegWithFormat_reg [VirtualRegWithFormat]
keep) (UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc)
-> UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$
                      (Loc -> Bool) -> UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc
forall {k} elt (key :: k).
(elt -> Bool) -> UniqFM key elt -> UniqFM key elt
filterUFM (VLoc -> Bool
inRegOrBoth (VLoc -> Bool) -> (Loc -> VLoc) -> Loc -> Bool
forall b c a. (b -> c) -> (a -> b) -> a -> c
. Loc -> VLoc
locWithFormat_loc) (UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc)
-> UniqFM VirtualReg Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$
                      UniqFM VirtualReg Loc
assig
                      -- This is non-deterministic but we do not
                      -- currently support deterministic code-generation.
                      -- See Note [Unique Determinism and code generation]
                let candidates :: [(Unique, Loc)]
candidates = UniqFM VirtualReg Loc -> [(Unique, Loc)]
forall {k} (key :: k) elt. UniqFM key elt -> [(Unique, elt)]
nonDetUFMToList UniqFM VirtualReg Loc
candidates'

                -- the vregs we could kick out that are already in a slot
                let compat :: RealReg -> Bool
compat RealReg
reg'
                      =  Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg'
                      RegClass -> RegClass -> Bool
forall a. Eq a => a -> a -> Bool
== RegClass
regclass
                    candidates_inBoth :: [(Unique, RealRegUsage, StackSlot)]
                    candidates_inBoth :: [(Unique, RealRegUsage, Int)]
candidates_inBoth
                        = [ (Unique
temp, RealReg -> Format -> RealRegUsage
RealRegUsage RealReg
reg Format
fmt, Int
mem)
                          | (Unique
temp, Loc (InBoth RealReg
reg Int
mem) Format
fmt) <- [(Unique, Loc)]
candidates
                          , RealReg -> Bool
compat RealReg
reg ]

                -- the vregs we could kick out that are only in a reg
                --      this would require writing the reg to a new slot before using it.
                let candidates_inReg :: [(Unique, RealRegUsage)]
candidates_inReg
                        = [ (Unique
temp, RealReg -> Format -> RealRegUsage
RealRegUsage RealReg
reg Format
fmt)
                          | (Unique
temp, Loc (InReg RealReg
reg) Format
fmt) <- [(Unique, Loc)]
candidates
                          , RealReg -> Bool
compat RealReg
reg ]

                let result :: RegM freeRegs ([instr], [RealReg])
result

                        -- we have a temporary that is in both register and mem,
                        -- just free up its register for use.
                        | (Unique
temp, (RealRegUsage RealReg
cand_reg Format
old_fmt), Int
slot) : [(Unique, RealRegUsage, Int)]
_ <- [(Unique, RealRegUsage, Int)]
candidates_inBoth
                        = do    spills' <- VirtualRegWithFormat
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
VirtualRegWithFormat
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualRegWithFormat
r SpillLoc
spill_loc RealReg
cand_reg [instr]
spills
                                let assig1  = UniqFM VirtualReg Loc -> Unique -> Loc -> UniqFM VirtualReg Loc
forall {k} (key :: k) elt.
UniqFM key elt -> Unique -> elt -> UniqFM key elt
addToUFM_Directly UniqFM VirtualReg Loc
assig Unique
temp (Loc -> UniqFM VirtualReg Loc) -> Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$ VLoc -> Format -> Loc
Loc (Int -> VLoc
InMem Int
slot) Format
old_fmt
                                let assig2  = UniqFM VirtualReg Loc -> VirtualReg -> Loc -> UniqFM VirtualReg Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM UniqFM VirtualReg Loc
assig1 VirtualReg
vr (Loc -> UniqFM VirtualReg Loc) -> Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$! SpillLoc -> RealRegUsage -> Loc
newLocation SpillLoc
spill_loc (RealReg -> Format -> RealRegUsage
RealRegUsage RealReg
cand_reg Format
vrFmt)

                                setAssigR $ toRegMap assig2
                                allocateRegsAndSpill reading keep spills' (cand_reg:alloc) rs

                        -- otherwise, we need to spill a temporary that currently
                        -- resides in a register.
                        | (Unique
temp_to_push_out, RealRegUsage RealReg
cand_reg Format
old_reg_fmt) : [(Unique, RealRegUsage)]
_
                                        <- [(Unique, RealRegUsage)]
candidates_inReg
                        = do
                                -- Spill what's currently in the register, with the format of what's in the register.
                                (spill_store, slot) <- RegWithFormat -> Unique -> RegM freeRegs ([instr], Int)
forall instr freeRegs.
Instruction instr =>
RegWithFormat -> Unique -> RegM freeRegs ([instr], Int)
spillR (Reg -> Format -> RegWithFormat
RegWithFormat (RealReg -> Reg
RegReal RealReg
cand_reg) Format
old_reg_fmt) Unique
temp_to_push_out

                                -- record that this temp was spilled
                                recordSpill (SpillAlloc temp_to_push_out)

                                -- Update the register assignment:
                                --  - the old data is now only in memory,
                                --  - the new data is now allocated to this register;
                                --    make sure to use the new format (#26542)
                                let assig1  = UniqFM VirtualReg Loc -> Unique -> Loc -> UniqFM VirtualReg Loc
forall {k} (key :: k) elt.
UniqFM key elt -> Unique -> elt -> UniqFM key elt
addToUFM_Directly UniqFM VirtualReg Loc
assig Unique
temp_to_push_out (Loc -> UniqFM VirtualReg Loc) -> Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$ VLoc -> Format -> Loc
Loc (Int -> VLoc
InMem Int
slot) Format
old_reg_fmt
                                let assig2  = UniqFM VirtualReg Loc -> VirtualReg -> Loc -> UniqFM VirtualReg Loc
forall key elt.
Uniquable key =>
UniqFM key elt -> key -> elt -> UniqFM key elt
addToUFM UniqFM VirtualReg Loc
assig1 VirtualReg
vr (Loc -> UniqFM VirtualReg Loc) -> Loc -> UniqFM VirtualReg Loc
forall a b. (a -> b) -> a -> b
$! SpillLoc -> RealRegUsage -> Loc
newLocation SpillLoc
spill_loc (RealReg -> Format -> RealRegUsage
RealRegUsage RealReg
cand_reg Format
vrFmt)
                                setAssigR $ toRegMap assig2

                                -- if need be, load up a spilled temp into the reg we've just freed up.
                                spills' <- loadTemp r spill_loc cand_reg spills

                                allocateRegsAndSpill reading keep
                                        (spill_store ++ spills')
                                        (cand_reg:alloc) rs


                        -- there wasn't anything to spill, so we're screwed.
                        | Bool
otherwise
                        = String -> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a. HasCallStack => String -> SDoc -> a
pprPanic (String
"RegAllocLinear.allocRegsAndSpill: no spill candidates\n")
                        (SDoc -> RegM freeRegs ([instr], [RealReg]))
-> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a b. (a -> b) -> a -> b
$ [SDoc] -> SDoc
forall doc. IsDoc doc => [doc] -> doc
vcat
                                [ String -> SDoc
forall doc. IsLine doc => String -> doc
text String
"allocating vreg:  " SDoc -> SDoc -> SDoc
forall doc. IsLine doc => doc -> doc -> doc
<> String -> SDoc
forall doc. IsLine doc => String -> doc
text (VirtualReg -> String
forall a. Show a => a -> String
show VirtualReg
vr)
                                , String -> SDoc
forall doc. IsLine doc => String -> doc
text String
"assignment:       " SDoc -> SDoc -> SDoc
forall doc. IsLine doc => doc -> doc -> doc
<> UniqFM VirtualReg Loc -> SDoc
forall a. Outputable a => a -> SDoc
ppr UniqFM VirtualReg Loc
assig
                                , String -> SDoc
forall doc. IsLine doc => String -> doc
text String
"format:           " SDoc -> SDoc -> SDoc
forall doc. IsLine doc => doc -> doc -> doc
<> Format -> SDoc
forall a. Outputable a => a -> SDoc
ppr Format
vrFmt
                                , String -> SDoc
forall doc. IsLine doc => String -> doc
text String
"freeRegs:         " SDoc -> SDoc -> SDoc
forall doc. IsLine doc => doc -> doc -> doc
<> String -> SDoc
forall doc. IsLine doc => String -> doc
text (freeRegs -> String
showRegs freeRegs
freeRegs)
                                , String -> SDoc
forall doc. IsLine doc => String -> doc
text String
"initFreeRegs:     " SDoc -> SDoc -> SDoc
forall doc. IsLine doc => doc -> doc -> doc
<> String -> SDoc
forall doc. IsLine doc => String -> doc
text (freeRegs -> String
showRegs (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform freeRegs -> freeRegs -> freeRegs
forall a. a -> a -> a
`asTypeOf` freeRegs
freeRegs))
                                ]
                        where showRegs :: freeRegs -> String
showRegs = [(RealReg, RegClass)] -> String
forall a. Show a => a -> String
show ([(RealReg, RegClass)] -> String)
-> (freeRegs -> [(RealReg, RegClass)]) -> freeRegs -> String
forall b c a. (b -> c) -> (a -> b) -> a -> c
. (RealReg -> (RealReg, RegClass))
-> [RealReg] -> [(RealReg, RegClass)]
forall a b. (a -> b) -> [a] -> [b]
map (\RealReg
reg -> (RealReg
reg, Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg)) ([RealReg] -> [(RealReg, RegClass)])
-> (freeRegs -> [RealReg]) -> freeRegs -> [(RealReg, RegClass)]
forall b c a. (b -> c) -> (a -> b) -> a -> c
. Platform -> freeRegs -> [RealReg]
forall freeRegs. FR freeRegs => Platform -> freeRegs -> [RealReg]
allFreeRegs Platform
platform

                RegM freeRegs ([instr], [RealReg])
result


-- | Calculate a new location after a register has been loaded.
newLocation :: SpillLoc -> RealRegUsage -> Loc
-- if the tmp was read from a slot, then now its in a reg as well
newLocation :: SpillLoc -> RealRegUsage -> Loc
newLocation (ReadMem Int
slot Format
memFmt) (RealRegUsage RealReg
r Format
_regFmt) =
  -- See Note [Use spilled format when reloading]
  VLoc -> Format -> Loc
Loc (RealReg -> Int -> VLoc
InBoth RealReg
r Int
slot) Format
memFmt

-- writes will always result in only the register being available
newLocation SpillLoc
_ (RealRegUsage RealReg
r Format
regFmt) = VLoc -> Format -> Loc
Loc (RealReg -> VLoc
InReg RealReg
r) Format
regFmt

-- | Load up a spilled temporary if we need to (read from memory).
loadTemp
        :: (Instruction instr)
        => VirtualRegWithFormat   -- the temp being loaded
        -> SpillLoc     -- the current location of this temp
        -> RealReg      -- the hreg to load the temp into
        -> [instr]
        -> RegM freeRegs [instr]

loadTemp :: forall instr freeRegs.
Instruction instr =>
VirtualRegWithFormat
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp (VirtualRegWithFormat VirtualReg
vreg Format
_fmt) (ReadMem Int
slot Format
memFmt) RealReg
hreg [instr]
spills
 = do
        -- See Note [Use spilled format when reloading]
        insn <- RegWithFormat -> Int -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
RegWithFormat -> Int -> RegM freeRegs [instr]
loadR (Reg -> Format -> RegWithFormat
RegWithFormat (RealReg -> Reg
RegReal RealReg
hreg) Format
memFmt) Int
slot
        recordSpill (SpillLoad $ getUnique vreg)
        return  $  {- mkComment (text "spill load") : -} insn ++ spills

loadTemp VirtualRegWithFormat
_ SpillLoc
_ RealReg
_ [instr]
spills =
   [instr] -> RegM freeRegs [instr]
forall a. a -> RegM freeRegs a
forall (m :: * -> *) a. Monad m => a -> m a
return [instr]
spills

{- Note [Allocated register formats]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
We uphold the following principle for the format at which we keep track of
alllocated registers:

  RF1. Writes redefine the format.

    When we write to a register 'r' at format 'fmt', we consider the register
    to hold that format going forwards.

    (In cases where a partial write is desired, the move instruction should
     specify that the destination format is the full register, even if, say,
     the instruction only writes to the low 64 bits of the register.
     See also Wrinkle [Don't allow scalar partial writes] in
     Note [Register formats in liveness analysis] in GHC.CmmToAsm.Reg.Liveness.)

  RF2. Reads from a register do not redefine its format.

    Generally speaking, as explained in Note [Register formats in liveness analysis]
    in GHC.CmmToAsm.Reg.Liveness, when computing the used format from a collection
    of reads, we take a least upper bound.

It is particularly important to get (RF1) correct, as otherwise we can end up in
the situation of T26411b, where code such as

  movsd .Ln6m(%rip),%v1
  shufpd $0,%v1,%v1

we start off with %v1 :: F64, but after shufpd (which broadcasts the low part
to the high part) we must consider that %v1 :: F64x2. If we fail to do that,
then we will silently discard the top bits in spill/reload operations.
-}

{- Note [Use spilled format when reloading]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
We always reload at the full format that a register was spilled at. The rationale
is as follows:

  1. If later instructions only need the lower 64 bits of an XMM register,
     then we should have only spilled the lower 64 bits in the first place.
     (Whether this is true currently is another question.)
  2. If later instructions need say 128 bits, then we should immediately load
     the entire 128 bits, as this avoids multiple load instructions.

For (2), consider the situation of #26526, where we need to spill around a C
call (because we are using the System V ABI with no callee saved XMM registers).
Before register allocation, we have:

  vmovupd %v1 %v0
  call ...
  movsd   %v0 %v3
  movhlps %v0 %v4

The contents of %v0 need to be preserved across the call. We must spill %v0 at
format F64x2 (as later instructions need the entire 128 bits), and reload it
later. We thus expect something like:

  vmovupd %xmm1    %xmm0
  vmovupd %xmm0    72(%rsp) -- spill to preserve
  call ...
  vmovupd 72(%rsp) %xmm0    -- restore
  movsd   %xmm0    %xmm3
  movhlps %xmm0    %xmm4

This is certainly better than doing two loads from the stack, e.g.

  call ...
  movsd   72(%rsp) %xmm0 -- restore only lower 64 bits
  movsd   %xmm0    %xmm3
  vmovupd 72(%rsp) %xmm0 -- restore the full 128 bits
  movhlps %xmm0    %xmm4

The latter being especially risky because we don't want to believe %v0 is 'InBoth'
with format F64. The risk is that, when allocating registers for the 'VMOVUPD'
instruction, we think our data is already in a register and thus doesn't need to
be reloaded from memory, when in fact we have only loaded the lower 64 bits of
the data.
-}